This invention relates generally to digital signal processing, and more particularly to a processing core that can be arranged to perform multiple complex signal processing functions.
Rapid advancements in digital multi-media applications is presenting increasingly more difficult challenges in designing the physical layer of communication equipment. Higher bandwidth and greater data throughput require faster and more efficient modems. For example, the processing of a real-time high quality MPEG video stream at 10.76 MHz or higher is likely to require dedicated hardware. This is due to the fact that many high speed applications, such as cable and terrestrial TV modems, ADSL modems, and ATM modems have base-band processing requirements in the order of Giga operations per second. As an added complexity, multiple communication standards exist, and many more are emerging.
In the prior art, adaptability has been achieved in several ways. One technique uses software configurable hardware. For example, field programmable gate arrays can implement modems that can accommodate different modulation formats for terrestrial, cable, telephone line, satellite, and wireless communications. This is an expensive solution not suitable for mass production. In another technique, multiple carrier recovery circuits are fabricated on a single chip. A particular circuit is selected based on a given type of demodulation format. As above, cost factors detract from this solution. General purpose microprocessors have been used. However, today""s high bandwidths make software solutions impractical.
In order to arrive at a particularly useful and versatile processing core, several widely used types of digital signal demodulators/receivers can be analyzed to determine commonly employed and recurring functions that are potential candidates for implementation in a processing core. In particular, various formats can respectively include receiver processing front-ends for Quadrature Amplitude Modulation (QAM)xe2x80x94FIG. 1, Orthogonal Frequency Division Multiplexing (OFDM)xe2x80x94FIG. 2, Vestigial Side Band (VSB)xe2x80x94FIG. 3, and Direct Sequence Spread Spectrum (DS-SS) Wideband Code Division Multiplexing (W-CDMA)xe2x80x94FIG. 4.
As shown in FIG. 1, a typical QAM demodulator front-end 100 includes two multipliers 111-112, two interpolators 121-122, an equalizer 130, and a carrier recovery circuit 140. The demodulator 100 takes a serial digital signal as input 101 and produces I and Q signals as output 109. A constant modulus algorithm is used during startup. Operating in either T or T/2 mode, the equalizer typically uses a delay line configured as complex, FIR filters with decision feed-back, feed-forward, or feed-back components having programmable lengths. Adaptive filters can have over a hundred taps requiring an equal number of terms in the computed vector products of the complex numbers.
As shown in FIG. 2, a OFDM receiver front-end 200 can include a serial-to-parallel converter (S/P) 210, an inverse Fast Fourier Transform (IFFT) 220, a parallel-to serial converter (P/S) 230, two multipliers 241-242, and an adder 250. The receiver takes a serial signal 201 as input and generates a demultiplexed serial signal as output 209. In order to map between time and space domains, generally, X(k)=xcexa3x(n)exe2x88x92j(2xcfx80/N), the FFT operates on blocks of, for example 2K or 8K terms.
As shown in FIG. 3, a VSB front-end 300 typically includes two multipliers 311-312, timing and carrier recovery circuits 320 and 330, and an equalizer 340. The equalizer here is similar to the QAM equalizer of FIG. 1, however, the VSB front-end uses a real mode equalizer, instead of a complex mode equalizer. In a real mode equalizer only the I-channel carries data, whereas in a complex mode equalizer, such as QAM, both the I- and Q-channels carry data. Input is provided on line 301, while the output appears on line 309. A normalized least means square method may be used for fast convergence. To realize both QAM and VSB modes, the processing core would have to switch between real and complex multiplications and additions.
As shown in FIG. 4, a W-CDMA receiver front-end 400 can include a down sampler 410, a root raised cosine filter (SCR) 420, and multiple instances of a despreader 430 and a coherence detector and rake combiner 440. A spread spectrum signal is the input, and a parallel signal can be fed to a channel detector 450. The down-sampler converts the input signal to base band, the SRC performs a FIR function, and element 440 equalizes the signal.
The analysis identifies a number of basic functions that could be implemented by arrangements of a common processing core. The basic functions are summarized in Table 1. In the table, the size and width are examples of typical implementations for digital video broadcast signal processing.
Therefore, it is desirable to construct a fundamental multi-functional circuit module or processing core that can be arranged alone, or in multiples to handle a number of different communication signal processing functions.
In accordance with the invention, a configurable communication signal processing core includes a set of particular arithmetic units and registers which are interconnected to operate in a plurality of different basic modes suitable for use in a number of digital modem functions.
Specifically, the processing core includes a multiplier having a first input and a second input and an output producing a product. An adder is connected to receive the product from the multiplier as a first input to produce a sum. A first register is connected to receive and store the sum from the adder, and to provide a second input for the adder in response to a clock signal. A second register is connected to receive and store the output of the first register in response to an inverse of the clock signal to enable the addition of two products in a single clock cycle.
In one embodiment, the processing core is fabricated on a single semiconductor chip having externally accessible signaling pins. In addition, the core can include a first multiplexer selecting the second input for the adder, a second multiplexer selecting the first input for the multiplier, and a third multiplexer selecting the second input for the multiplier.